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data bulletin cmx644a ? ? ? ? 2000 mx-com, inc. www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480197.006 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective companies. bell 212a and v.22 modem with call progress and dtmf preliminary information features ? bell 212a and v.22 compatible modem ? 1200bps full duplex operation (2 or 4 wire) ? uart for start/parity/stop bit processing ? non-uart operating mode ? software adjustable tx and rx levels ? programmable group delay equalizer ? answer/originate tone generator/detector ? call progress tone detection ? integrated dtmf encoder ? line reversal and ring detector ? hook switch relay driver ? flexible xtal/master clock selection ? simple serial control interface ? zero-power standby mode ? 3.0v to 5.0v operation applications ? telephone telemetry systems ? remote utility meter reading ? security systems ? payphones ? cable-tv set-top boxes ? industrial control systems ? electronic cash terminals ? vending machines unscrambler psk modulator tx filter tone generator 1 local analog loopback control & data registers carrier, call progress, answer tone detectors registers rx filter psk demodulator ring & line reversal detect tx programmable equalizer command oscillator clocks scrambler xtal/clk cs serial clk passive hybrid network 2 or 4 wire line rx programmable equalizer tx+ v bias rx- rxampout rd rt rlydrv xtal rx+ tone generator 2 rx data serial interface local digital loopback tx data reply registers irq tx txin- tx- uart the cmx644a bell 212a / v.22 modem provides full duplex 1200bps data signaling suitable for telephone- based information and telemetry systems where low power operation is desired. bell 212a / v.22 signaling delivers fast-call set-up times and robust, error resistant, transmission in 2- or 4-wire line circuits. a rich set of important additional functions enhances end product value while reducing size. these include: integrated dtmf encoder for dial out functions, single tone encoder for ?melody? generation, answer tone generator/detector, line reversal and ring detector for ?waking? up a sleeping c, adjustable tx and rx gain, and a low impedance pull down output for hook relay control. the addition of the answer tone generator/detector and call progress tone detector makes the set-up of a telephone call much easier for the host c to accomplish. very low power telemetry and data collection applications are supported by the cmx644a?s ?zero power? standby mode in which the device will detect telephone line ringing voltage or line voltage reversal events. the cmx644a is pin compatible with the cmx624 bell 202 / v.23 modem, operates with a supply voltage between 3.0v and 5.5v and is available in the following packages: 24-pin ssop (cmx644ad5), 24-pin soic (cmx644ad2), and 24-pin pdip (CMX644AP4).
bell 212a / v.22 modem with call progress and dtmf 2 cmx644a preliminary information ? ? ? ? 2000 mx-com, inc. www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480197.006 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective companies. contents section page 1 block diagram ............................................................................................................... 3 2 signal list .................................................................................................................... .. 4 3 external components.................................................................................................... 6 4 general description....................................................................................................... 7 4.1 ?c-bus? serial interface ...................................................................................................... .7 4.2 uart........................................................................................................................ ............8 4.3 software description ......................................................................................................... ...9 4.3.1 write-only ?c-bus? registers ................................................................................................ .9 4.3.2 write-only register descriptions............................................................................................ 9 4.3.3 read only ?c-bus? registers .............................................................................................. 16 5 application notes ........................................................................................................ 20 5.1 line interface............................................................................................................... .......20 5.1.1 4-wire line interface....................................................................................................... ..... 20 5.1.2 2-wire line interface....................................................................................................... ..... 21 5.2 ring detector interface ......................................................................................................2 2 5.3 software protocol for transmitting psk data bytes ..........................................................23 5.4 software protocol for receiving psk data bytes ..............................................................23 5.5 handling underflow and overflow conditions....................................................................24 6 performance specification ......................................................................................... 26 6.1 electrical performance ....................................................................................................... 26 6.1.1 absolute maximum ratings ................................................................................................. 26 6.1.2 operating limits ........................................................................................................... ........ 26 6.1.3 operating characteristics .................................................................................................. .. 27 6.1.4 timing .................................................................................................................... .............. 29 6.2 packaging................................................................................................................... ........31 mx-com, inc. reserves the right to change specifications at any time and without notice.
bell 212a / v.22 modem with call progress and dtmf 3 cmx644a preliminary information ? ? ? ? 2000 mx-com, inc. www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480197.006 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective companies. 1 block diagram figure 1: block diagram
bell 212a / v.22 modem with call progress and dtmf 4 cmx644a preliminary information ? ? ? ? 2000 mx-com, inc. www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480197.006 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective companies. 2 signal list cmx644a d2/d5/p4 signal pin no. name type description 1 xtal output the inverted output of the on-chip oscillator. 2 xtal/clock input the input to the on-chip oscillator, for external xtal circuit or clock. 3 serial clock input the ?c-bus? serial clock input. this clock, produced by the controller, is used for the transfer timing of commands to and from the device. 4 command data input the ?c-bus? serial data input from the controller. data is loaded into this device in 8-bit bytes, msb (b7) first, and lsb (b0) last, synchronized to the serial clock. 5 reply data tri-state the ?c-bus? serial data output to the controller. the transmission of reply data bytes is synchronized to the serial clock under control of the cs input. this 3-state output is held at high impedance when not sending data to the controller. 6 cs input chip select. the ?c-bus? data loading control function: this input is provided by the controller. data transfer sequences are initiated, completed or aborted by the cs signal. 7 irq output this output indicates an interrupt condition to the controller by going to a logic ?0?. this is a ?wire-orable? output, enabling the connection of up to 8 peripherals to 1 interrupt port on the controller. this pin has a low impedance pull-down to logic ?0? when active and a high impedance when inactive. an external pull-up resistor is required. 8 tx output the output of the transmit gain control. 9 tx+ output the output of the line driver amplifier. 10 txin- input the inverting input to the line driver amplifier. 11 tx- output the inverted output of the line driving amplifier. pins tx+ and tx- provide symmetrical outputs for use with a balanced load to give sufficient tx line signal levels even at low v dd . 12 v ss power the negative supply rail (ground). 13 v bias output a bias line for the internally circuitry, held at v dd /2. this pin must be decoupled by a capacitor mounted close to the device pins. 14 rlydrv output an open-drain output for controlling a relay. 15 rx+ input the non-inverting input of the receive op-amp. 16 rx- input the inverting input of the receive op-amp. 17 rxampout output the output of the receive op-amp. 18 rt bi-directional open-drain output and schmitt trigger input forming part of the ring or line polarity reversal detector. an external resistor to v dd and a capacitor to v ss should be connected to rt to filter and extend the rd input signal. 19 rd input to the ring or line polarity reversal detector. 20, 21, 22 - n/c no connections should be made to these pins.
bell 212a / v.22 modem with call progress and dtmf 5 cmx644a preliminary information ? ? ? ? 2000 mx-com, inc. www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480197.006 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective companies. cmx644a d2/d5/p4 signal pin no. name type description 23 a/d cap output the reference voltage for the internal a to d of the receiver. this pin must be decoupled by a capacitor mounted close to the device pins. 24 v dd power the positive supply rail. levels and thresholds within the device are proportional to this voltage. should be decoupled to v ss by a capacitor mounted close to the device pins. this device is capable of detecting and decoding small amplitude signals. it is recommended that the printed circuit board be laid out with a ground plane in the cmx644a area to provide a low impedance connection between the v ss pin and the v dd and v bias decoupling capacitors. the receive path should be protected as much as possible from extraneous signals. table 1: signal lists
bell 212a / v.22 modem with call progress and dtmf 6 cmx644a preliminary information ? ? ? ? 2000 mx-com, inc. www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480197.006 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective companies. 3 external components 1 c1 c2 c5 c4 r1 x1 xtal xtal/clock c-bus to/from c tx line interface. see 5.1 rx line interface. see 5.1 to/from ring detector. see 5.2 serial clock command data reply data cs irq tx rx+ rlydrv relay drive rx- rxampout rt rd v dd v dd txin- tx+ tx- v ss 2 3 4 cmx644a d5/d2/p4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 v bias n/c n/c a/d cap n/c c3 figure 2: recommended external components r1 note 1 100k ? 1 % c1, c2 18pf 20 % c3, c4, 0.1 f 20 % c5 1 f 20 % x1 3.6864mhz, 7.372800mhz or 11.0592mhz tolerances for resistors and capacitors are as indicated unless otherwise stated. table 2: recommended external components for typical application recommended external component notes on xtal osc and clock dividers 1. r1 should be selected so that the irq pin has returned to its normal (high) state before cs pin goes high. 2. frequency and timing accuracy of the cmx644a is determined by the clock present at the xtal/clock pin. this may be generated by the on-chip oscillator inverter using the external components c1, c2 and x1 of figure 2, or may be supplied from an external source to the xtal/clock input. if the clock is supplied from an external source, c1, c2 and x1 should not be fitted. 3. the on-chip oscillator is turned off in the ' zero-power ' mode. 4. if the clock is provided by an external source that is not always running, then the ' zero-power ' mode must be set when the clock is not available. failure to observe this rule may cause a rise in the supply current drawn by cmx644a. 5. for best results, a crystal oscillator design should drive the clock inverter input with signal levels of at least 40 % of v dd , peak to peak. tuning fork crystals generally cannot meet this requirement. to obtain crystal oscillator design assistance, please consult your crystal manufacturer.
bell 212a / v.22 modem with call progress and dtmf 7 cmx644a preliminary information ? ? ? ? 2000 mx-com, inc. www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480197.006 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective companies. 4 general description 4.1 ?c-bus? serial interface this block provides for the transfer of data and control or status information between the cmx644a?s internal registers and the c over the ?c-bus? serial bus. each ' c-bus ' transaction consists of a single register address byte sent from the c, as illustrated in figure 3, which may be followed by either of: 1. a single data byte sent from the c to be written into one of the cmx644a?s write only registers, as illustrated in figure 4. 2. a single byte of data read out from one of the cmx644a?s read only registers, as illustrated in figure 5. data sent from the c on the command data line is clocked into the cmx644a on the rising edge of the serial clock input. reply data sent from the cmx644a to the c is valid when the serial clock is high. the interface is compatible with the most common c serial interfaces such as sci, spi and microwire, and may be easily implemented with general purpose c i/o pins controlled by a simple software routine. see figure 15 for detailed ?c-bus? timing requirements. cs serial clock command data address (01 hex = reset) = level not important hi-z reply data 7 654 321 0 figure 3: c-bus transactions (single byte from c) cs serial clock command data address hi-z data to cmx644a reply data 7 654 321 0 7 654 321 0 figure 4: c-bus transactions (one address and one data byte from c) cs serial clock hi-z address data from cmx644a command data reply data 7 654 321 0 7 654 321 0 figure 5: c-bus transactions (one address byte from c and one reply byte from cmx644a)
bell 212a / v.22 modem with call progress and dtmf 8 cmx644a preliminary information ? ? ? ? 2000 mx-com, inc. www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480197.006 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective companies. 4.2 uart this block connects the c, via the ?c-bus? interface, to the received data from the psk demodulator and to the transmit data input to the psk modulator. as part of the uart function, this block can be programmed to convert data that is to be transmitted from 7 or 8-bit bytes to asynchronous data characters, adding start and stop bits, and - optionally - a parity bit to the data before passing it to the psk modulator. in the receive direction the uart can extract data bits from asynchronous characters coming from the psk demodulator, stripping off the start and stop bits, and performing an optional parity check on the received data, before passing the result, via the ?c-bus?, to the c. bits 0-5 of the uart mode register control the number of stop and data bits and the parity options for both receive and transmit directions. data to be transmitted should be loaded by the c into the tx data byte register when the tx data ready bit (bit 1) of the fla g s register goes high. it will then be treated by the tx uart block in one of two ways, depending on the setting of bit 5 of the uart mode register: 1. if bit 5 of the uart mode register is ?0? (?sync? mode) then the 8 bits from the tx data byte register will be transmitted sequentially lsb (d0) first. 2. if bit 5 of the uart mode register is ?1? (?async? mode) then the 7 or 8 bits will be transmitted as asynchronous data characters according to the following format: one start bit (space). 7 or 8 data bits from the tx data byte register (d0-d6 or d0-d7) as determined by bit 0 of the uart mode register. lsb (d0) transmitted first. optional parity bit (even or odd parity) as determined by bits 1 and 2 of the uart mode register. zero, one or two stop bits (mark) as determined by bits 3 and 4 of the uart mode register. in both cases data will only be transmitted if bit 6 of the tx psk mode register is set to ?1?. failure to load the tx data byte register with a new value when required will result in bit 2 (tx data underflow) of the fla g s register being set to ?1? and a continuous mark (?1?) signal will then be transmitted until a new value is loaded into tx data byte register. tx data register loaded: tx data psk signal: t del t load t ufl tx data ready flag bit: tx data underflow flag bit: d0 d0 start start p'ty stop d1 d2 d3 d4 d5 d6 d7 figure 6: transmit uart function (async) received data from the psk demodulator goes into the receive part of the uart block, where it is handled in one of two ways depending on the setting of bit 5 of the uart mode register: 1. if bit 5 of the uart mode register is ?0? (?sync? mode) then the receive part of the uart block will simply take 8 consecutive bits from the demodulator and transfer them to the rx data byte register (the first bit going into the d0 position). 2. if bit 5 of the uart mode register is ?1? (?async? mode) then the received data output of the psk demodulator is treated as asynchronous characters each comprising: a start bit (space). 7 or 8 data bits as determined by bit 0 of the uart mode register. these bits will be placed into the rx data byte register with the first bit received going into the d0 position. an optional parity bit as determined by bits 1 and 2 of the uart mode register. if parity is enabled (bit 2 of the uart mode register = ?1?) then bit 7 of the fla g s register will be set to ?1? if the received parity is incorrect. any number of stop bits (mark).
bell 212a / v.22 modem with call progress and dtmf 9 cmx644a preliminary information ? ? ? ? 2000 mx-com, inc. www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480197.006 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective companies. bit 3 (rx data ready) of the fla g s register will be set to ?1? every time a new received value is loaded into the rx data byte register. if the previous contents of the rx data byte register had not been read out over the ?c-bus? before the new value is loaded from the uart then bit 4 (rx data overflow) of the fla g s register will also be set to ?1?. rx data register read: rx data psk signal: t rdy rx data ready flag bit: rx data overflow flag bit: d0 d0 start start p'ty stop d1 d2 d3 d4 d5 d6 d7 figure 7: receive uart function (async) the c-bus serial clock should be fast enough to ensure that an rx data ready interrupt is serviced completely within a time which is less than 8-bit times at 1200 baud, i.e. less than 6.67ms. 4.3 software description 4.3.1 write-only ?c-bus? registers register name hex address/ command bit 7 (d7) bit 6 (d6) bit 5 (d5) bit 4 (d4) bit 3 (d3) bit 2 (d2) bit 1 (d1) bit 0 (d0) g eneral reset $ 01 n/a n/a n/a n/a n/a n/a n/a n/a set-up $ e0 0 relay drive detect det1 detect det0 loop- back: l1 loop- back: l0 xtal frq: x1 xtal frq: x0 tx tones $ e1 tone sel tone / notone dtmf / modem tones dtmf / sn g l d3 d2 d1 d0 g ain blocks $ e2 tx g ain t g 3 tx g ain t g 2 tx g ain t g 1 tx g ain t g 0 rx g ain r g 3 rx g ain r g 2 rx g ain r g 1 rx g ain r g 0 tx data byte $ e3 d7 d6 d5 d4 d3 d2 d1 d0 uart mode $ e4 0 0 sync/ async stop bits b stop bits a parity enable parity odd/ even data bits 8/7 tx psk mode $ e7 0 tx- enab scramb unlock scramb enable equal et1 equal et0 enable hi/lo band rx psk mode $ e8 0 cpbw select de- scramb unlock de- scramb enable equal er1 equal er0 enable hi/lo band irq mask bits $ ee rx parity rin g detect detect rx data over- flow rx data ready tx data under- flow tx data ready un- scram mark table 3: write only 'c-bus' register 4.3.2 write-only register descriptions 4.3.2.1 general reset ($01) the reset command has no data attached to it. application of the g eneral reset sets all write-only register bits to ?0?.
bell 212a / v.22 modem with call progress and dtmf 10 cmx644a preliminary information ? ? ? ? 2000 mx-com, inc. www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480197.006 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective companies. 4.3.2.2 set-up register ($e0) (bit 7) reserved for future use. this bit should be set to ?0?. relay drive (bit 6) this bit controls a low impedance pull-down transistor connected to the rlydrv pin to assist with the operation of an ?off-hook relay?. when set to ?1? the transistor acts as a pull-down and will sink current. when set to ?0? the pin is in a high impedance state. detect det1 and det0 (bits5and4) these 2 bits control the operation of the receiver filter in order to facilitate the detection of the following signals as shown in table 5. loopback l1 and l0 (bits3and2) these 2 bits control internal signal paths such that loopback tests can be performed. function is according to table 6. xtal frq x1 and x0 (bits1and0) these two bits control the internal primary clock dividers to allow for a choice of 3 crystal frequencies. they can also be set to put the device into ?zero power? mode: in this mode all functions are powersaved, except for the ?c-bus? and the ring detector. in ?zero power? the crystal oscillator is disabled and the bias resistor chain is disconnected from the supplies. note: when the device is brought out of ?zero power? mode, the software should allow at least 20ms for the crystal oscillator to re-start and for the bias capacitor to re-charge, before proceeding with any further device functions. the function is provided according to table 7. table 4: set-up register ($e0) det1 (bit 5) det0 (bit 4) required rx hi/lo band setting (register $e8, bit 0) detection mode 0 0 as required for rx psk psk carrier 01lo =' 0 ' call progress 10hi =' 1 ' answer tone 1 1 as required for rx psk detectors off note: rx psk mode register enable bit should be set to ' 1 ' for answer tone and call progress detection. table 5: detect (det1 and det0) l1 (bit 3) l0 (bit 2) 0 0 normal device operation: no loopback. 01 local analog loopback: the output of the tx gain block is routed to the input of the receiver gain block. (the connection between the receiver op-amp and gain block is broken). 10 local digital loopback: data is loaded into the tx data byte register in the usual way via the ?c-bus? when indicated by the tx data ready flag. this digital data is internally retimed serially to the modem bit-rate and is then clocked into the receiver buffer. when the receiver buffer is full the rx data ready flag will be set and the data can then be read out of rx data byte register via the ?c-bus?. 1 1 reserved for future use. table 6: loopback l1 and l0 x1 (bit 1) x0 (bit 0) crystal / mode 0 0 ?zero power? 0 1 3.6864mhz crystal 1 0 7.3728mhz crystal 1 1 11.0592mhz crystal table 7: xtal freq x1 and x0
bell 212a / v.22 modem with call progress and dtmf 11 cmx644a preliminary information ? ? ? ? 2000 mx-com, inc. www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480197.006 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective companies. 4.3.2.3 tx tones register ($e1) this register is used to transmit both dtmf and modem progress tones. tonesel (bit 7) this bit selects the ?answer tone? frequency in the receive detector. a ?0? selects 2225hz and a ?1? selects 2100hz. tone/notone (bit 6) this bit should be used to begin and end the transmission of tones once the required frequency has been programmed. when set to ?1? the tone will be transmitted ; when set to ?0? a notone (bias voltage) will be generated. dtmf/modem tones (bit 5) when this bit is set to ?1? the device is configured for dtmf. when it is set to ?0? the device is configured to transmit modem progress tones. dtmf/sngl (bit 4) for normal dtmf operation this bit should be set to ?0?. for test purposes it can be set to ?1? in order to select the tone frequencies individually. table 8: tx tones register ($e1) the following table shows the settings required for transmitting dtmf (bit 5 should be set to ?1?. bits 6 and 7 should be operated as described above). d3 d2 d1 d0 lower freq. (hz) (setting bit 4 = 0) upper freq. (hz) (setting bit 4 = 0) keypad symbol single tone freq. (hz) (setting bit 4 = 1) 0 0 0 0 941 1633 d 1633 0 0 0 1 697 1209 1 1209 0 0 1 0 697 1336 2 1336 0 0 1 1 697 1477 3 1477 0 1 0 0 770 1209 4 1209 0 1 0 1 770 1336 5 1336 0 1 1 0 770 1477 6 1477 0 1 1 1 852 1209 7 1209 1 0 0 0 852 1336 8 852 1 0 0 1 852 1477 9 852 1 0 1 0 941 1336 0 941 1 0 1 1 941 1209 * 941 1 1 0 0 941 1477 # 941 1 1 0 1 697 1633 a 697 1 1 1 0 770 1633 b 770 1 1 1 1 852 1633 c 852 table 9: dtmf tx settings the following table shows the settings required for transmitting modem progress tones. (set bit 4 to ?0? and bit 5 to ?0?. bits 6 and 7 should be operated as described earlier). d3 d2 d1 d0 frequency (hz) tone description 0000 550 g uard 0 0 0 1 1300 calling 0 0 1 0 1800 g uard 0 0 1 1 2100 answer 0 1 0 0 2225 answer table 10: modem progress tx tones settings
bell 212a / v.22 modem with call progress and dtmf 12 cmx644a preliminary information ? ? ? ? 2000 mx-com, inc. www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480197.006 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective companies. 4.3.2.4 gain blocks register ($e2) bits 0 to 3 (r g 0tor g 3) control the levels of the receiver input gain block according to the following table: rg3 (bit 3) rg2 (bit 2) rg1 (bit 1) rg0 (bit 0) gain (db) 0 0 0 0 -4.70 0 0 0 1 -3.46 0 0 1 0 -2.12 0 0 1 1 -0.96 01000.00 01010.87 01101.64 01112.36 10003.08 10013.69 10104.22 10114.76 11005.27 11015.78 11106.21 11116.58 table 11: gain blocks register ($e2) the gain should be set in a calibration procedure in order to trim out the effects of any component tolerances which may give rise to a variation in the carrier detect threshold levels. bits4to7(t g 0tot g 3) control the levels of the transmit path gain block according to the following table: tg3 (bit 7) tg2 (bit 6) tg1 (bit 5) tg0 (bit 4) gain (db) 0000off(outputatbias) 0001 -5.6 0010 -5.2 0011 -4.8 0100 -4.4 0101 -4.0 0110 -3.6 0111 -3.2 1000 -2.8 1001 -2.4 1010 -2.0 1011 -1.6 1100 -1.2 1101 -0.8 1110 -0.4 1111 0.0 table 12: control levels for the tx path gain block
bell 212a / v.22 modem with call progress and dtmf 13 cmx644a preliminary information ? ? ? ? 2000 mx-com, inc. www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480197.006 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective companies. 4.3.2.5 tx data byte register ($e3) each byte of data to be transmitted should be loaded into this register. it is double buffered, thus giving the user up to 8 bit periods to load in the next 8 bits. each byte represents 4 lots of 2 consecutive bits (dibits) with the most significant dibits being loaded first (taking bit 7 of this register as being the most significant). the data is reversed so that it is transmitted least significant dibit first. these dibits represent a transmitted phase change according to the following table: symbol values phase change 00 +90 01 0 11 +270 10 +180 table 13: tx data byte register ($e3) note: the left-hand digit of the dibit is the one occurring first in the data stream as it enters the modulator portion of the modem after the scrambler. 4.3.2.6 uart mode register ($e4) (bit 7 and bit 6) reserved for future use. these bits should be set to ?0?. sync/async (bit 5) when this bit is ?0?, data will be transmitted and received in normal 8 bit mode without modification. when this bit is ?1?, data will be transmitted and received with one start bit (?0?) and 7/8 bits, odd/even parity, 0 or 1 or 2 stop bits according to the remainder of the bits in this register. prior to handshaking the uart mode register needs bit 5 cleared for synchronous operation. after the handshaking procedure has completed bit 5 the uart mode register should be set for asynchronous data transfer. the remaining bits of this register should be configured to be compatible with the modem you are talking to. the minimum number of stop bits only applies to the transmitter, the receiver does not require any defined number of stop bits. stop bits a and b (bits4and3) the minimum number of stop bits transmitted after each data byte plus parity is defined by table 15. the receiver does not require any defined number of stop bits. parity enable (bit 2) when this bit is ?1? an extra bit is added after the data to indicate the parity of that data. when set to ?0?, parity is disabled. this bit affects both transmitter and receiver. parity odd/even (bit 1) when this bit is ?1? the parity is set odd, and when this bit is ?0? the parity is set even. this bit affects both transmitter and receiver. data bits 8/7 (bit 0) when this bit is ?1? the data is set to transmit and receive 7 bits, i.e. bits 0-6. when this bit is ?0? the normal 8 bits of data is programmed. this bit affects both transmitter and receiver. table 14: uart mode register ($e4) stop bits a stop bits b number of stop bits 00 0 01 1 10 1 11 2 table 15: stop bits (a and b)
bell 212a / v.22 modem with call progress and dtmf 14 cmx644a preliminary information ? ? ? ? 2000 mx-com, inc. www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480197.006 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective companies. 4.3.2.7 tx psk mode register ($e7) (bit 7) reserved for future use. this bit should be set to ?0?. tx- enab (bit 6) this bit enables or powersaves the inverted output of the line driving amplifier (tx-). when set to ?1? tx- is enabled ; together with tx+ these outputs provide sufficient complementary output to drive a line even at low v dd . when set to ?0? the tx- output is powersaved, reducing the total supply current for applications in which a single-ended output is sufficient. scramb unlock (bit 5) when this bit is set to ?1? the scrambler will check for sequences of 64 consecutive ones at its output (caused by scrambler lockup) and once detected it will invert the next input to the scrambler. when this bit is set to ?0? the lock-up prevention is disabled. scramb enable (bit 4) when this bit is set to ?1? the tx data is passed through the scrambler. when it is set to ?0? the scrambler is bypassed. equal et1 and et0 (bits3and2) these 2 bits control the level of equalization applied to the transmitted signal according to table 17. see figure 8 and figure 9 for the typical equalizer responses. the equalizer is automatically powersaved when both et1 and et0 are set to ' 0 ' . enable (bit 1) when this bit is set to ?1? the internal output of the psk modulator is enabled. when it is set to ?0? the internal output of the psk modulator is set to v bias . associated flags are only set when this bit is ?1?. hi/lo band (bit 0) this bit determines whether the transmitted psk signal should occupy the low channel (900hz - 1500hz) or the high channel (2100hz - 2700hz). when the bit is set to ?0? the low channel is selected. when it is set to ?1? the high channel is selected. table 16: tx psk mode register ($e7) et1 (bit 3) et0 (bit 2) transmitter equalization 0 0 no equalization 0 1 low 10medium 11high table 17: equal et1 and et0
bell 212a / v.22 modem with call progress and dtmf 15 cmx644a preliminary information ? ? ? ? 2000 mx-com, inc. www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480197.006 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective companies. 4.3.2.8 rx psk mode register ($e8) (bit 7) reserved for future use. this bit should be set to ?0?. cpbw select bit 6 when this bit is set to ?1? the call progress detector bandwidth is approximately 300hz ? 620hz. when this bit is set to ?0? the call progress detector bandwidth is approximately 400hz ? 620hz. de-scramb unlock (bit 5) when this bit is set to ?1? the de-scrambler will check for sequences of 64 consecutive ones at its input and once detected it will invert the next output from the de-scrambler. when this bit is set to ?0? the all ones detection is disabled - it should be set as such until the handshaking sequence is complete. de-scramb enable (bit 4) when this bit is set to ?1? the rx data is passed through the de-scrambler. when it is set to ?0? the de-scrambler is bypassed. equal er1 and er0 (bits3and2) these 2 bits control the level of equalization applied to the received signal according to table 19. see figure 8 and figure 9 for the typical equalizer responses. the equalizer is automatically powersaved when et1 and et0 are set to ?no equalization? (?0?, ?0?). enable (bit 1) when this bit is set to ?1? the psk receiver is enabled. when it is set to ?0? the receiver is disabled. associated flags are only set when this bit is ?1?. hi/lo band (bit 0) this bit determines whether the received psk signal should be filtered and derived from the low channel (900hz - 1500hz) or the high channel (2100hz - 2700hz). when this bit is set to ?0? the low channel is selected. when it is set to ?1? the high channel is selected. table 18: rx psk mode register ($e8) er1 (bit 3) er0 (bit 2) receiver equalization 0 0 no equalization 0 1 low 1 0 medium 11 high table 19: equal er1 and er2
bell 212a / v.22 modem with call progress and dtmf 16 cmx644a preliminary information ? ? ? ? 2000 mx-com, inc. www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480197.006 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective companies. 4.3.2.9 irq mask bits ($ee) this register is used to control the interrupts (irqs) as described below: rx parity mask (bit 7) when this bit is set to ?1? it enables an interrupt that occurs when the rx parity flag (bit 7, fla g s register, $ ef) changes from ?0? to ?1? i.e. there is an rx parity error. when this bit is ?0? the interrupt is masked. ring detect mask (bit 6) when this bit is set to ?1? it enables an interrupt that occurs when rin g detect chan g eflag(bit6,fla g s register, $ ef) changes from ?0? to ?1?. when this bit is ?0? the interrupt is masked. detect mask (bit 5) when this bit is set to ?1? it enables an interrupt that occurs when detect flag (bit 5, fla g s register, $ ef) changes from ?0? to ?1?. when this bit is ?0? the interrupt is masked. rx data overflow mask (bit 4) when this bit is set to ?1? it enables an interrupt that occurs when rx data overflow flag (bit 4, fla g s register, $ ef) changes from ?0? to ?1?. when this bit is ?0? the interrupt is masked. rx data ready mask (bit 3) when this bit is set to ?1? it enables an interrupt that occurs when rx data ready flag (bit 3, fla g s register, $ ef) changes from ?0? to ?1?. when this bit is ?0? the interrupt is masked. tx data underflow mask (bit 2) when this bit is set to ?1? it enables an interrupt that occurs when tx data underflow flag (bit 2, fla g s register, $ ef) changes from ?0? to ?1?. when this bit is ?0? the interrupt is masked. tx data ready mask (bit 1) when this bit is set to ?1? it enables an interrupt that occurs when tx data ready flag (bit 1, fla g s register, $ ef) changes from ?0? to ?1?. when this bit is ?0? the interrupt is masked. unscram mark mask (bit 0) when this bit is set to ?1? it enables an interrupt that occurs when unscram mark flag (bit 0, fla g s register, $ ef) changes from ?0? to ?1?. when this bit is ?0? the interrupt is masked. table 20: irq mask bits ($ee) 4.3.3 read only ?c-bus? registers register name hex address/ command bit 7 (d7) bit 6 (d6) bit 5 (d5) bit 4 (d4) bit 3 (d3) bit 2 (d2) bit 1 (d1) bit 0 (d0) rx data byte $ ea d7 d6 d5 d4 d3 d2 d1 d0 tones detect $ ec 1 rin g detect call pr g rss detect carrier detect answer detect 00 un-scram mark detect fla g s $ ef rx parity rin g detect chan g e detect rx data over- flow rx data ready tx data under- flow tx data ready un-scram mark table 21: read only 'c-bus' registers
bell 212a / v.22 modem with call progress and dtmf 17 cmx644a preliminary information ? ? ? ? 2000 mx-com, inc. www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480197.006 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective companies. 4.3.3.1 rx data byte register ($ea) this register contains the last byte of data received. it is updated every 8 bits at the same time as the rx data ready flag is set. the rx data byte register is double buffered, thus giving the user up to 8 bit periods to read the data before it is overwritten by the next byte. each received phase change is decoded into 2 bits (dibits). the incoming dibits fill this register starting at the most significant end (bits 7 and 6). symbol values phase change 00 +90 01 0 11 +270 10 +180 table 22: rx data byte register ($ea) note: the left-hand digit of the dibit will be the more significant of the 2 bits when located in this register. 4.3.3.2 tones detect register ($ec) this register provides information as to the presence or absence of various signaling conditions detected by the receiver. a logic ?1? indicates that the signaling condition is present ; a logic ?0? indicates that it is absent. (bit 7) this bit will be set to ?1?. ring detect level (bit 6) indicates the status of the ring/line polarity reversal detector circuit. the logic level of this bit represents the level of the internal ?rin g detect? node (see figure 1). call prgrss detect (bit 5) indicates the detection of call progress tones in the selected band. (300hz to 620hz or 400hz to 620hz). carrier detect (bit 4) indicates the detection of a carrier in the received channel. answer detect (bit 3) bits 2 and 1 indicates the detection of an answer tone of 2100hz or 2225hz. these bits will be set to ?0?. unscram mark detect (bit 0) indicates the detection of unscrambled binary one in the received data for a period of time of 160ms. table 23: tones detect register ($ec) note: detect bits 5, 4 and 3 are mutually exclusive and are enabled by the setting of the detect det1 or det0 bits (set-up registers bits 5 and 4). all the detect bits in the tones detect register - except for rin g detect (bit 6) - require the rx psk mode register enable bit to be set to ?1?.
bell 212a / v.22 modem with call progress and dtmf 18 cmx644a preliminary information ? ? ? ? 2000 mx-com, inc. www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480197.006 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective companies. 4.3.3.3 flags register ($ef) the flags register is used to indicate when the device requires attention. when a flag becomes set to ?1? and its corresponding mask bit is ?1? then an interrupt ( irq ) will be generated. immediately after the flags register has been read, all the bits will be reset to ?0? and consequently any interrupt will be cleared. rx parity flag (bit 7) when this bit is ?1? the received parity is in error. when this bit is ?0? the received parity is correct. ring detect change flag (bit 6) when rin g detect (tones detect register, bit 6) changes state, this bit will be set to ?1?. detect flag (bit 5) when any of the following bits - call pr g rss detect, carrier detect or answer detect (tones detect register bits 5, 4, 3) - change state, this bit will be set to ?1?. rx data overflow flag (bit 4) if received data is not read out of the device within the 8-bit window of rx data ready going high, then this bit will be set to ?1? to indicate an error condition. rx data ready flag (bit 3) when a full byte of data is received and is available in the rx data byte register, this bit will be set to ?1?. there is then an 8-bit window during which the rx data byte register must be read. tx data underflow flag (bit 2) if data is not loaded into the tx data byte register within the 8-bit window of tx data ready going high, then this bit will be set to ?1? to indicate an error condition. tx data ready flag (bit 1) when the tx data buffer is ready to receive a new byte of data, this bit will be set to ?1?. there is then an 8-bit window for the loading of the tx data byte register. unscram mark flag (bit 0) when the unscram mark detect bit (tones detect register bit 0) changes state, this bit will be set to ?1?. table 24: flags register ($ef)
bell 212a / v.22 modem with call progress and dtmf 19 cmx644a preliminary information ? ? ? ? 2000 mx-com, inc. www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480197.006 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective companies. 0.0e+00 1.0e-04 2.0e-04 3.0e-04 4.0e-04 5.0e-04 6.0e-04 7.0e-04 8.0e-04 9.0e-04 1.0e-03 1.1e-03 1.2e-03 1.3e-03 1.4e-03 1.5e-03 1.6e-03 1.7e-03 1.8e-03 1.9e-03 2.0e-03 600 700 800 900 1000 1100 1200 1300 1400 1500 1600 1700 1800 fr e que nc y ( hz ) group delay (secs) lowband low medium high figure 8: transmit/receive equalizer responses: lowband 0.0e+00 1.0e-04 2.0e-04 3.0e-04 4.0e-04 5.0e-04 6.0e-04 7.0e-04 8.0e-04 9.0e-04 1.0e-03 1.1e-03 1.2e-03 1.3e-03 1.4e-03 1.5e-03 1.6e-03 1.7e-03 1.8e-03 1.9e-03 2.0e-03 1800 1900 2000 2100 2200 2300 2400 2500 2600 2700 2800 2900 3000 frequency (hz) group delay (secs) highband low medium high figure 9: transmit/receive equalizer responses: highband the cmx644a utilizes two internal equalizers - one is configured for the high band, the other for the low band. the transmit and receive paths will be internally switched through the equalizer appropriate to their hi/lo band settings. in the event of both transmit and receive paths being set to the same band, both equalizers will be bypassed.
bell 212a / v.22 modem with call progress and dtmf 20 cmx644a preliminary information ? ? ? ? 2000 mx-com, inc. www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480197.006 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective companies. 5 application notes 5.1 line interface a line interface circuit is needed to provide dc isolation between the modem and the line, to perform line impedance termination, and to set the correct transmit and receive signal levels. 5.1.1 4-wire line interface figure 10 shows an interface circuit for use with a 600 ? 4-wire line. the line terminations are provided by r10 and r15, while r11 and r13 should be selected to give the desired transmit and receive levels. when v dd = 5.0v, the gain of the receive input amplifier (r12/r11) should be 6db (times 2.0) plus whatever additional gain is required to compensate for the loss of the input transformer. at other values of v dd the amplifier gain should be multiplied by the ratio v dd /5.0. thus for r12 = 100k ? : () () 2.0 x loss r transforme input 5.0/v x 100k r11 dd ? = where the ?input transformer loss? = (rx level on 4-wire line) / (level at point a of figure 10). assuming a transformer loss of about 1db, r11 should be 47k ? at v dd = 5.0v, and 68k ? at 3.3v. the value of the resistor r11 is optimized for the carrier detect level. increasing the input gain (by reducing the value of r11) will improve modem sensitivity. a c10 r11 r12 r10 r13 r14 r15 c11 c13 rx tx 4-wire line 1:1 1:1 tx rx+ rx- rxampout txin- tx+ tx- v bias v bias v bias cmx644a + - + - + - c12 figure 10: 4-wire line interface circuit note: the relay circuit, ac and dc loads and line protection are not shown for clarity. r10 600 ? r14 100k ? c10 100nf r11 see text r15 600 ? c11 330pf r12 100k ? c12 330pf r13 see text c13 100nf resistors 1 % , capacitors 20 % . table 25: 4-wire line interface circuit in the transmit direction, the level on the 4-wire line is determined by the level at the tx pin, the gain of the output buffer amplifier, a loss of nominally 6db due to the line termination resistor r15, and the loss in the transformer.
bell 212a / v.22 modem with call progress and dtmf 21 cmx644a preliminary information ? ? ? ? 2000 mx-com, inc. www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480197.006 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective companies. the tx pin signal level is proportional to v dd . it is also affected by the setting of the transmitter programmable gain block. assuming that the tx programmable gain block is set to -2db (giving a psk signal level of -4db with respect to 775mv rms at the tx pin when v dd = 5.0v) and that there is 1db loss in the transformer, then: dbm ) 5.0 v ( lo g x 20 ) r13 r14 x (2 lo g x 20 1) 6 (4 - level line wire - 4 psk tx dd 10 10 + + + + = for example, to generate a nominal tx psk line level of -10dbm, r13 should be 180k ? when v dd = 5.0v, falling to 120k ? at 3.3v. 5.1.2 2-wire line interface figure 11 shows an interface circuit suitable for connection to a 600 ? 2-wire line. the circuit also shows how a relay may be driven from the rlydrv pin. note that when the cmx644a is powered from less than 5.0v, buffer circuitry will be required to drive a 5v relay. c13 r11 r12 r13 r17 r16 r14 r15 c11 c12 2-wire line 1:1 tx rx+ rlydrv rx- rxampout txin- tx+ tx- v bias v bias cmx644a + - + - + - c14 figure 11: 2-wire line interface circuit note: ac and dc loads and line protection are not shown for clarity r11 see text r15 600 ? c11 330pf r12 100k ? r16 120k ? c12 330pf r13 see text r17 100k ? c13 10nf r14 100k ? c14 100nf resistors 1 % , capacitors 20 % unless otherwise specified table 26: 2-wire line interface circuit this circuit includes a 2-wire to 4-wire hybrid circuit, formed by r11, r15, r16, r17, c13 and the impedance of the line itself, which ensures that the modem receive input and transmit output paths are both coupled efficiently to the line, while minimizing coupling from the modem?s transmit signal into the receive input. the values of r11 and r13 should be calculated in the same way as for the 4-wire interface circuit of figure 10. note: the component values r17 and c13 depend on the transformer characteristics and should be adjusted to achieve a flat frequency response measured at the rxo pin.
bell 212a / v.22 modem with call progress and dtmf 22 cmx644a preliminary information ? ? ? ? 2000 mx-com, inc. www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480197.006 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective companies. 5.2 ring detector interface figure 12 shows how the cmx644a may be used to detect the large amplitude ringing signal received at the start of an incoming telephone call. the ring signal is usually applied at the subscriber ' s exchange as an ac voltage inserted in series with one of the telephone wires and will pass through either c20 and r20 or c21 and r21 to appear at the top end of r22 (point x in figure 12) in a rectified and attenuated form. the signal at point x is further attenuated by the potential divider formed by r22 and r23 before being applied to the cmx644a rd input. if the amplitude of the signal appearing at rd is greater than the input threshold (vt hi ) of schmitt trigger ' a ' then the n transistor connected to rt will be turned on, pulling the voltage at rt to v ss by discharging the external capacitor c22. the output of the schmitt trigger ' b ' will then go high, setting bit 6 (rin g detect) of the tones detect register. the minimum amplitude ringing signal that is certain to be detected is [] rms rms hi v signal ring . min v 707 . 0 23 r 23 r 22 r 20 r vt 7 . 0 = ? ? ? ? ? ? ? ? + + + where vt hi is the high-going threshold voltage of the schmitt trigger a with r20 - 22 all 470k ? as figure 12, then setting r23 to 68k ? will guarantee detection of ringing signals of 40vrms and above for v dd over the range 3.0 to 5.5v. 2-wire telephone line rd cmx644a to tones detect register q1 v dd d1 - 4 c20 c22 r20 r21 r22 r23 r24 c21 rt tones detect register bit 6 (ring detect) flags register bit 5 (ring detect change) bridge rectifier output (x) ring signal vt hi v ss v ss vt hi a b x rt figure 12: ring signal detector interface circuit r20,21,22 470k ? c20,21 0.1 f r23 see text c22 0.33 f r24 470k ? d1 - 4 1n4004 resistors 1 % , capacitors 20 % table 27: ring signal detector interface circuit
bell 212a / v.22 modem with call progress and dtmf 23 cmx644a preliminary information ? ? ? ? 2000 mx-com, inc. www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480197.006 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective companies. if the time constant of r24 and c22 is large enough then the voltage on rt will remain below the threshold of the ' b ' schmitt trigger for the duration of a ring cycle. the time for the voltage on rt to charge from v ss towards v dd can be derived from the formula ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? = dd rt v v - 1 ln rc t as the schmitt trigger high-going input threshold voltage (vt hi ) has a minimum value of 0.56 x v dd , then the schmitt trigger b output will remain high for a time of at least 0.821 x r24 x c22 following a pulse at rd. the values of r24 and c22 given in figure 12 (470k ? and 0.33 f) give a minimum rt charge time of 100ms, which is adequate for ring frequencies of 10hz or above. note that the circuit will also respond to a telephone line voltage reversal. if necessary the c can distinguish between a ring signal and a line voltage reversal by measuring the time that bit 6 of the tones detect register (rin g detect) is high. 5.3 software protocol for transmitting psk data bytes in order to transmit psk data, the following steps should be followed. for clarity, not all bit settings are described here (but hi/lo band, equalization, g uard tones, number of stop bits, etc. should be set as appropriate). 1. program setup register for correct crystal frequency. wait at least 20ms if device was previously in ?zero power? mode before proceeding. 2. set tx g ain block ( g ain blocks register $ e2) to required gain. set uart mode. 3. load first data byte into tx data byte register ( $ e3). 4. read fla g s register ( $ ef) in order to clear it. 5. set irq mask bits register ( $ ee bits 2 and 1) to allow appropriate interrupts (tx data underflow and tx data ready). note: if an underflow occurs, continuous mark (?1?) will be transmitted. 6. set enable bit (tx psk mode register $ e7) to ?1?. the first byte of data will now be transmitted by the device. 7. wait for a tx data ready generated interrupt (read fla g s to check and clear the irq). 8. load next tx data byte. 9. g oto7. note: the transmission should be terminated by setting the enable bit (tx psk mode register) to ?0?. 5.4 software protocol for receiving psk data bytes 1. with the device out of ?zero power? mode, set up all receiver-related functions: g ain, hi/lo band, equalization, uart mode, etc. 2. perform a dummy read of the rx data byte register ( $ ea) and discard the result. 3. read fla g s register ( $ ef) in order to clear it. 4. set irq mask bits register ( $ ee bits 7, 4 and 3) to allow appropriate interrupts (rx parity, rx data overflow and rx data ready). 5. set enable bit (rx psk mode register $ e8) to ?1?. 6. wait for an rx data ready generated interrupt (read fla g s to check and clear the irq). 7. read rx data byte ( $ ea). 8. g oto5.
bell 212a / v.22 modem with call progress and dtmf 24 cmx644a preliminary information ? ? ? ? 2000 mx-com, inc. www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480197.006 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective companies. 5.5 handling underflow and overflow conditions if the rx data byte register has not been read before the next byte of rx data is received, then the rx data overflow flag will be set and the rx data byte register will hold the most recent byte of received data. the rx data ready flag will remain set if the fla g s register is not read before the overflow condition occurs. both rx data ready and rx data overflow flags are reset upon reading the fla g s register, and are not set again until after the rx data byte register has been read (i.e. the overflow condition has been cleared). if the tx data byte register is not written to before the last byte of tx data is sent, then the tx data underflow flag will be set and the tx data will then consist of continuous mark ( " 1 " ), which will normally be scrambled, until new data is loaded into the tx data byte register. the tx data ready flag will remainsetifthefla g s register is not read before the underflow condition occurs. both tx data ready and tx data underflow flags are reset upon reading the fla g s register, and are not set again until after the tx data byte register has been loaded with new data (i.e. the underflow condition has been cleared). c-bus transactions to handle underflow and overflow conditions are shown in the timing diagram of figure 13. note that allowance should be made for c-bus latency (tdel and tload) when changing register settings. e.g. to change the number of tx stop bits transmitted with all subsequent data (stop bits a and b), first wait until the tx data ready flag is set. if this check is not made, then the number of stop bits in the tx data byte that is currently being sent will be changed.
bell 212a / v.22 modem with call progress and dtmf 25 cmx644a preliminary information ? ? ? ? 2000 mx-com, inc. www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480197.006 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective companies. tx data (analog - psk) rx data (analog - psk) tx ready flag rx ready flag c-bus cs c-bus irq read byte 1 from rx da ta read byte 4 from rx da ta read flags read byte 2 from rx da ta note: c-bus timing not shown to scale load tx da ta with byte 1 load tx da ta with byte 2 command data reply data tx under- flow flag rx over- flow flag 833s typ. bit period = load tx da ta with byte 3 general reset command t rdy t rdy byte 1 byte 1 byte 2 byte 2 byte 3 (lost) byte 3 (lost) byte 4 byte 4 mark mark flags not read flags not read flags read flags read t load t load flags not read flags not read flags read flags read t ufl t ufl t del t del byte 1 byte 1 byte 2 byte 2 byte 3 byte 3 mark mark figure 13: async mode (rx and tx)
bell 212a / v.22 modem with call progress and dtmf 26 cmx644a preliminary information ? ? ? ? 2000 mx-com, inc. www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480197.006 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective companies. 6 performance specification 6.1 electrical performance 6.1.1 absolute maximum ratings exceeding these maximum ratings can result in damage to the device. min. max. units supply (v dd -v ss )-0.37.0v voltage on any pin to v ss -0.3 v dd +0.3 v current into or out: v dd -50 50 ma v ss -50 50 ma any other pin -20 20 ma current sink into rlydrv pin 0 50 ma d2 / p4package total allowable power dissipation at t amb = 25c 800 mw derating above 25c 13 mw/c above 25c storage temperature -55 125 c operating temperature -40 85 c d5 package total allowable power dissipation at t amb = 25c 550 mw derating above 25c 9 mw/c above c storage temperature -55 125 c operating temperature -40 85 c 6.1.2 operating limits correct operation of the device outside these limits is not implied. nominal xtal frequencies are 3.6864mhz, 7.372800mhz, 11.0592mhz. min max. units supply (v dd -v ss )2.75.5v operating temperature -40 85 c xtal frequency -100 100 ppm
bell 212a / v.22 modem with call progress and dtmf 27 cmx644a preliminary information ? ? ? ? 2000 mx-com, inc. www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480197.006 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective companies. 6.1.3 operating characteristics for the following conditions unless otherwise specified: v dd = 2.7v at t amb = 25c and v dd = 3.0v to 5.5v at t amb = -40to85c. 0dbm corresponds to 775mv rms . notes min. typ. max. units dc parameters i dd (?zero power?) 2 1 a i dd (operating at v dd = 3.0v) 2 3.2 4.0 ma i dd (operating at v dd = 3.0v) with equalization enabled 24.6ma logic ?1? input level 5 70 % -v dd logic ?0? input level 5 30 % v dd logic input leakage current (v in = 0to v dd ), (excluding xtal/clock input) -1.0 1.0 a output logic ?1? level (i oh = 360a) v dd -0.4 v output logic ?0? level (i ol = 360a) 0.4 v irq output ?off? state current (v out = v dd ) 1.0 a schmitt trigger input high-going threshold (vt hi ) (see figure 14) 0.56v dd 0.56v dd +0.6v v schmitt trigger input low-going threshold (vt lo ) (seefigure14) 0.44v dd -0.6v 0.44v dd v relay driver pull-down on resistance (v dd = 5.0v, 50ma maximum load current) 37.0 ? xtal/clock input pulse width (?high? or ?low?) 3 40 ns input impedance (at 100hz) 10 m ? g ain (input = 1mv rms at 1khz) 20 db ac parameters transmitter (at tx pin) guard tones level (below psk) of 550hz -3.0 db level (below psk) of 1800hz -6.0 db frequency accuracy -0.25 +0.25 % psk output transmitted level 1, 4, 8 -3.0 -2.0 -1.0 dbm distortion 2.0 5.0 % dtmf output transmitted level: high group 1, 4 -2.0 -1.0 0 dbm twist (high group - low group levels) 4 2.0 db distortion 2.0 5 % frequency accuracy -0.25 +0.25 %
bell 212a / v.22 modem with call progress and dtmf 28 cmx644a preliminary information ? ? ? ? 2000 mx-com, inc. www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480197.006 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective companies. notes min. typ. max. units receiver dynamic range (v dd = 5.0v) 45 db carrier detect threshold: will decode 1, 6 -43 dbm threshold: will not decode 1, 6 -48 dbm hysteresis 7 2.0 db response time (delay) 20 50 ms de-response time (hold) 20 50 ms answer tone detector threshold: will decode 1, 6 -43 dbm threshold: will not decode 1, 6 -48 dbm response time (delay) 20 50 ms de-response time (hold) 20 50 ms decode bandwidth must decode 2.0 % must not decode 6.0 % call progress detector effective bandwidth 9 300/400 620 hz threshold: will decode 1, 6 -43 dbm threshold: will not decode 1, 6 -48 dbm response time (delay) 20 50 ms de-response time (hold) 20 50 ms programmable gain blocks rx gain block nominal range -4.70 +6.58 db (step size: see register description) step accuracy -0.5 +0.5 db tx gain block nominal range -5.6 0.0 db step size 0.4 db step accuracy -0.2 +0.2 db notes: 1. at v dd = 5.0v only. signal levels or currents are proportional to v dd . 2. not including any current drawn from the modem pins by external circuitry. 3. timing for an external input to the clock/xtal pin. 4. tx g ain block set to 0db and measured with a pure tone or dtmf tone pair, without equalization. 5. excluding rd, rt and xtal/clock pins. 6. rx g ain block nominally set to 0db but adjusted if necessary for component tolerances. measurement point for threshold levels is prior to receive input amplifier circuit (point a on figure 11), with external components setting gain to 9db. detector levels measured with a pure tone. 7. hysteresis may be increased, if required, by adding one step (increasing the gain of) to the rx g ain block when a signal is detected and by removing this step when the signal is no longer detected. 8. measured with a 511-bit pseudorandom sequence. 9. depending on the setting of the cpbw select bit in the rx psk mode register
bell 212a / v.22 modem with call progress and dtmf 29 cmx644a preliminary information ? ? ? ? 2000 mx-com, inc. www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480197.006 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective companies. 0 0.5 1 1.5 2 2.5 3 3.5 4 2.5 3 3.5 4 4.5 5 5.5 v dd v in vt hi vt lo figure 14: typical schmitt trigger input voltage vs. v dd 6.1.4 timing 6.1.4.1 uart timing tx timings (see figure 6) notes min. typ. max. units t del tx delay from tx data loaded 1 0.833 ms t load tx output to tx reload signal 1 0.833 ms t ufl tx parity to tx underflow flag set 1 1.667 ms table 28: tx timings - transmit uart function (async) rx timings (see figure 7) notes min. typ. max. units t rdy parity to rx data ready flag set 1 1.667 ms table 29: tx timings - receiver uart function (async) uart timing notes 1. measured without equalization.
bell 212a / v.22 modem with call progress and dtmf 30 cmx644a preliminary information ? ? ? ? 2000 mx-com, inc. www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480197.006 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective companies. 6.1.4.2 c-bus timing ?c-bus? timings (see figure 15) notes min. typ. max. units t cse cs -enable to clock-high time 100 ns t csh last clock-high to cs -high time 100 ns t loh clock-low to reply output enable time 0 ns t hiz cs -high to reply output 3-state time 1.0 s t csoff cs -high time between transactions 1.0 s t nxt inter-byte time 200 ns t ck clock-cycle time 200 ns t ch serial clock-high time 100 ns t cl serial clock-low time 100 ns t cds command data set-up time 75 ns t cdh command data hold time 25 ns t rds reply data set-up time 75 ns t rdh reply data hold time 0 ns note: these timings are for the latest version of the ?c-bus? as embodied in the cmx644a, and allow faster transfers than the original ?c-bus? timings provided in mx-com?s publication doc. # 20480060.001. table 30 ?c-bus? timings cs hi-z = level not important or undefined serial clock t cse t nxt t ck t cl t cds t rds t cdh t rdh 70% v dd 30% v dd t ch t ck t csoff t csh t hiz t loz command data command data serial clock reply data reply data 76543 21 0 76543 21 0 76543 21 0 figure 15: ?c-bus? timing
bell 212a / v.22 modem with call progress and dtmf 31 cmx644a preliminary information ? ? ? ? 2000 mx-com, inc. www.mxcom.com tel: 800 638 5577 336 744 5050 fax: 336 744 5054 doc. # 20480197.006 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective companies. 6.2 packaging 0.597 (15.16) package tolerances a b c e h typ. max. min. dim. j p x w t y k l 0.105 (2.67) 0.093 (2.36) 0.419 (10.64) 45 7 0 10 0.050 (1.27) 0.046 (1.17) 0.613 (15.57) 0.299 (7.59) 0.050 (1.27) 0.016 (0.41) 0.390 (9.90) 0.020 (0.51) 0.003 (0.08) 0.009 (0.23) 0.0125 (0.32) 0.013 (0.33) 0.020 (0.51) 0.036 (0.91) 0.286 (7.26) z note : all dimensions in inches (mm.) angles are in degrees 5 5 pin 1 a b x p j y c h k e l t w z alternative pin location marking figure 16: 24-pin soic (d2) mechanical outline: order as part no. cmx644ad2 note : all dimensions in inches (mm.) angles are in degrees package tolerances a b c e h typ. max. min. dim. j p x t y z l 0.079 (2.00) 0.066 (1.67) 0.312 (7.90) 0 7 4 8 9 10 0.037 (0.95) 0.328 (8.33) 0.213 (5.39) 0.026 (0.65) 0.022 (0.55) 0.301 (7.65) 0.008 (0.21) 0.002 (0.05) 0.005 (0.13) 0.009 (0.22) 0.010 (0.25) 0.015 (0.38) 0.318 (8.07) 0.205 (5.20) x c h p j y e z l t pin 1 a b figure 17: 24-pin ssop (d5) mechanical outline: order as part no. cmx644ad5 note : all dimensions in inches (mm.) angles are in degrees package tolerances a b c e e1 h typ. max. min. dim. j j1 p y t k l 0.220 (5.59) 0.555 (14.04) 0.670 (17.02) 7 0.160 (4.05) 1.270 (32.26) 0.151 (3.84) 0.100 (2.54) 0.121 (3.07) 0.600 (15.24) 0.590 (14.99) 0.625 (15.88) 0.015 (0.38) 0.045 (1.14) 0.008 (0.20) 0.015 (0.38) 0.015 (0.38) 0.023 (0.58) 0.040 (1.02) 0.065 (1.65) 0.066 (1.67) 0.074 (1.88) 1.200 (30.48) 0.500 (12.70) h k l j1 j p c b a pin1 t e e1 y figure 18: 24-pin pdip (p4) mechanical outline: order as part no. CMX644AP4

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